CIC Global 2025

Augusto Castro joined Cadence in November 2022, as part of Jasper’s Platform team. He holds a MSc. Degree from the University of Sao Paulo, where his research focused on uncertainty estimation of deep learning models. Since last year, his work involves bringing generative AI to formal verification flows in Jasper. 

Samir leads AI in Silicon Systems Design and Advanced Memory Systems development at Micron Technology He guides Micron’s university engagements for systems and design. He is a member of the Dean’s Advisory Council for College of Engineering at The Ohio State University. As an executive champion of the Micron’s Center of Excellence at Georgia Institute of Technology, he serves on the advisory board of the Department of Computer and Electrical Engineering.

Prior to Micron, Samir founded SCUTI AI, a startup focused on next generation data center infrastructure for deep learning applications. Samir and the SCUTI team transitioned to Micron designing and developing data center persistent memory (3DXP) products where they launched the world’s fastest SSD in record time. Prior to SCUTI AI, Samir was VP of Engineering at SanDisk leading the industry transition to an All-Flash data center with full stack solutions. Samir also held senior leadership roles at Qumu Corporation delivering secure cloud services video products, and at Seagate Technology in hard disk drive-based storage products. Samir earned a doctorate from The Ohio State University, specializing in control systems and signal processing. He has been recognized by the university with the E.G. Bailey award for entrepreneurship as an outstanding alumnus.

Gianluca Iaccarino is the Robert Bosch Chair and Professor of the Mechanical Engineering Department at Stanford University. He received his PhD in Italy from the Politecnico di Bari (Italy) in 2005, and joined the faculty at Stanford in 2007. Since 2014, he has been the Director of the PSAAP Center at Stanford, funded by the US Department of Energy focused on multiphysics simulations, uncertainty quantification, data science and exascale computing. He received the US Association for Computational Mechanics (ACM) Thomas Hughes Medal, the Presidential Early Career Award for Scientists and Engineers (PECASE) award and is a Fellow of American Physical Society (APS) and Senior Fellow of American Institute for Aeronautics and Astronautics (AIAA).

Thamara Andrade is a Senior Principal Engineer with over a decade of experience on the Jasper Formal Verification team. In the past 18 months, she has spearheaded projects integrating and leveraging generative AI within the Jasper flow. A self-proclaimed problem solver, Thamara is passionate about learning new things and sharing her knowledge with others. (And yes, this bio was AI-generated—talk about practicing what you preach!) 

Zheng REN obtained his Ph.D. degree from the GREMAN Laboratory, CNRS, University of Tours on Micro-electronics and Semiconductor in 2018. He also worked in STMicroelectronics before joining Cadence. He is now a principal software engineer in Spectre Device team and working closely with the main foundries on device modeling.

Yuan-Kai Pei is a software engineering director in Taiwan with 28 years of EDA experience in back-end development. His team is responsible for Virtuoso schematic migration, concurrent layout, performance diagnostic tools and more. He is also the contact person for Virtuoso performance issues and local support for companies like TSMC and MediaTek. Yuan-Kai earned a master’s degree in CS from the University of Texas at Austin, and a bachelor’s degree in EE from National Taiwan University. He started his career in 1997 as a software developer at Xilinx in San Jose. He joined Cadence Taiwan in 2003, SpringSoft in 2008, and rejoined Cadence in 2012.

Yoni Ashkenazi joined cadence on the 15th of June 2008, which means he has been working for cadence for 17 years and 3 days.

All those years he has been working on projects related to Debug – starting with CAST – a project that aimed at automating the debug process, continued with Indago reverse debugger, which later became Verisium Debug – a debugger that supports Xcelium and Palladium.

Yoni Managed a big part of Verisium Debug R&D team until 2022 when he decided to go back to be an individual contributor. He is now heading the work on Debug Advisor which leverages LLM capabilities for debug work.

He also finds it very strange to write his own biography and to refer to himself in third person.

Dr. Xu Wang is a Software Engineering Director at Cadence Design Systems, Inc. He creates solutions that enable the design of photonic integrated circuits and electronic-photonic systems. He received his PhD from the University of British Columbia. 

Xiuxin Li joined in the Cadence in 2019 with the master’s degree from Beijing University of Posts and Telecommunications. After joining in the Cadence, Xiuxin focused on the thermal analysis, and developed the thermal map project alone with the python script at the beginning of her career in Cadence, and finally Xiuxin co-worked with the Virtuoso team to integrate the thermal map into the Virtuoso. Then she gradually focuses on the whole flow development of thermal analysis and collaborates with the Celsius/EMIR team to make the thermal analysis solid and improve the thermal analysis performance step by step. She is currently a Principal Software Engineer and the project leader of the thermal analysis.

Xinyu Liu joined Cadence in 2020 after graduating with a bachelor’s degree from The Ohio State University. Before that, he interned at Ohio Supercomputer Center. He is currently a lead software engineer on the Virtuoso ADE team in the San Jose office. He contributed to the Simulation Manager of ADE, which improved reliability and performance by decoupling the GUI from the job management process, especially for long-running and large-scale simulation runs.

Xinyang joined Cadence as a product validation engineer since 2020 after earning a master’s degree in electrical and computer engineering from University of Michigan, Ann Arbor. As a member of 3D-IC PV team, he is working on improving the quality of Integrity 3D-IC Platform and its interface with other product tools such as Celsius and Allegro.

Xiaoyan Y. Z. Xiong is a Software Architect in Sigrity R&D US Group at Cadence Design System, Inc. Dr Xiong has over 15 years’ experience in developing advanced electromagnetic analysis and simulation methods. She worked as Assistant Professor in Zhejiang University, Research Assistant Professor in The University of Hong Kong in 2018 and 2016, respectively. Dr Xiong received her Ph. D degree from The University of Hong Kong, Hong Kong, in 2015.

Xiaobo Wang is a Software Architect at Cadence Design System. He received a Ph.D. degree from the University of Delaware in 2010, a master's degree, and a bachelor's degree from the University of Science and Technology of China. He has over 18 years’ experience working on computational electromagnetics, optimization algorithms, and is currently focusing on optimization and machine learning methods for IC designs. 

Shaowei Chiu is a Lead Software Engineer in the Conformal ECO team at Cadence, where he has contributed since 2022. He specializes in runtime optimization, ECO algorithms, and parallel computing. With a master's degree in computer science from National Chiao Tung University, Shaowei brings both academic rigor and practical innovation to his work. Outside of engineering, he enjoys badminton, coffee, and weightlifting.

Weifeng Gu is a software engineer in DSG 3DIC team. He joined Cadence as a regular FTE in 2019 and rejoined in 2022. He has been involved in the development and maintenance of FP, AUTO FP and SDP. Recently, he has focused on 3DIC-related projects such as 3D Early Floorplan Synthesis (3DEFS) and 3DIC Prototyping. Weifeng graduated from Shanghai University with a bachelor’s degree in computer science.

Vivek Nandakumar is a Senior Design Architect at Cadence, Silicon Solutions Group, specializing in performance modeling and analysis of DDR memory controllers and system-level architectures. He has held prior roles at Qualcomm (Nuvia), Synopsys, and AMD, with experience in SoC performance. He holds a Ph.D. in Electrical and Computer Engineering from UC Santa Barbara, where he researched CPU-GPU systems, 3D-stacked processors, and energy-efficient architectures, and has authored multiple research publications in these areas. 

Vishesh is an architect of application engineering, working with Cadence since last 12 year. He leads an AE team, responsible for enabling Noida and Hyderabad based customers on custom IC flows front to back. Vishesh has done his masters in Microelectronics from BITS Pilani and having 20 years of industry experience. Prior to joining Cadence, he has worked on custom design implementation, flows and methodology development with start-up and multinationals. He has collaborated with customer and R&D on many projects from brainstorming on idea to production quality tool. He has also presented papers and posters in multiple industry leading conferences, winning best paper awards at user track of VLSI Design conference in 2021 and once poster gladiator nominee at DAC. Vishesh is also a proud recipient of Trailblazer Award by EMT at CIC 2023.

Vipul Jain received the M.E degree in electronic system from Indian Institute of Science, Bangalore, India, in 2019. From 2019 to 2022, he worked on different IO protocols like LVDS, SLVS and Comparators for 5G Digital beamforming with Analog Devices, Bangalore, India. From 2022 to 2016 he has been working on high-speed memory interfaces in Cadence Design systems as a lead design engineer. He holds 4 granted and filed patents and has 2 IEEE published papers.

Vikram Samal has 17 years of experience in technology, specializing in the Microsoft ecosystem. He has been with Cadence for ten years and currently holds the position of Senior IT Architect. In this role, he oversees Cadence's SharePoint implementations, focusing on building new solutions that enhance collaboration and productivity within the company. Vikram earned a Bachelor of Technology degree in Electronics and Telecommunications from India.

Victor Raposo is a Product Validation Engineer for Verisium Debug and has been contributing to Cadence since 2024. He holds a degree in Electronic and Computer Engineering and a Master’s in Microelectronics, both from UFRJ. Throughout his academic and professional journey, Victor has published multiple papers in the field of microelectronics. Based in Belo Horizonte, Brazil, he is passionate about automation, digital cameras, and optimization. 

Varun Singh is a Senior Principal Software Engineer in the FED Test R&D group, where he leads the DFT IP development team. He joined Cadence in 2022 in the SSG group (formerly Tensilica/IPG) as one of the initial designers on the NOC R&D project which is now productized as Janus NOC System IP.

He holds a master’s degree in electrical engineering from University of Southern California and has industrial experience designing and leading system IP and SOC development for more than 8 years.

Dr. Rosario is a Sr. Principal Software Engineer at Cadence Design Systems, where he leads development and optimization of the Xtensa Neural Network Compiler (XNNC). With five years of experience at Cadence, he specializes in compilation techniques for machine learning and deep learning applications.

Dr. Rosario holds a PhD in Computer Science from UNICAMP, Brazil, during which he also spent time as a visiting researcher at IST in Portugal, focusing on neural network parallelism. His research has earned multiple accolades, including Best Paper and Best PhD Thesis awards.

He is an active contributor to prominent open-source projects at the intersection of compiler technology and artificial intelligence, helping drive performance and efficiency in next-generation AI systems.

Vamshi Krishna Nagilla joined Cadence (INVECAS) in 2015. He holds a master’s degree in VLSI from Jawaharlal Nehru Technological University (JNTU), obtained in 2011. Currently, he is pursuing a part-time PhD at BITS Pilani, Hyderabad Campus, with a research focus on "Strategies for Verification of NoC-based Multi-Processor Architectures." 

With approximately 15 years of industry experience in Functional Verification, Mr. Vamshi Krishna Nagilla is presently serving as the SoC Verification Lead for the Front-end team in the Silicon Realization Group (SRG).

Tomas Schweizer is a Software Engineering Director, leading the DevOps and Documentation Team for VFS/SVG. He holds a PMP certification and has an MBA in Project Management, along with a specialization in Software Engineering from PUC Minas. Tomas also has a degree in Mathematics and Computational Mathematics. Since 2007, he has been active in the Information Technology field, possessing various certifications and extensive experience in the entire software development lifecycle. With 17 years of experience in the Software Engineering area, Tomas has been with Cadence for over 8 years. Currently based in Munich, Bavaria, Germany. He is passionate about Automation, DevOps, and productivity, as well as team building, and is dedicated to driving innovation and efficiency within his team.

Tevin Cheng received his B.S. and M.S. degrees in Computer Science from National Tsing Hua University. He joined Avanti in 2001, which later merged with Synopsys, where he worked on R&D for DRC in physical verification tools. In 2010, he moved to Cadence Taiwan and relocated to the U.S. in 2012. He is currently a Senior Principal Software Engineer on the Pegasus Team, focusing on solving complex issues in multiple-patterning and dummy fill utilities.

Tadhg Creedon is a Distinguished Engineer based in the Cadence Galway, Ireland office.

Tadhg came to Cadence in 2022 via the acquisition of CréVinn Teoranta, an ASIC Design Services and IP provider company established in 2002, where Tadhg was CEO and founder. He has been designing ASICs since their introduction in 1983.

Tadhg works for the DDR group consulting on various memory controller projects in the areas of overall architecture, CDC, error handling, design guidelines and various other technical topics.

Sureshkumar Gajelli is a Senior Design Engineering Manager at SSG TPG RLC SW DSP group at Cadence, Pune. He holds Master’s degree from Indian Institute of Technology Kanpur, completed in 2013.

With over a decade of experience in signal processing, his work spans audio, image/video codecs, and classical signal processing. Since joining Cadence in 2016, he has been part of the development and productization of the RLC (ConnX/MathX), Fusion, and recent Vision DSPs. His team also plays a pivotal role in enabling the software libraries to cover the rich instruction set architecture offered by these platforms.

Srinivas Gudla is a Senior Principal Software Engineer in Characterization team in DSG group. He joined Cadence in 2015 and in last 9 years, worked on development of multiple products like “Verisium”, “Helium” and “Liberate” in SVG, HSV and DSG groups respectively. He holds a bachelor’s degree in computer science from JNTU, India and master’s degree in computer science from Georgia Institute of Technology. Prior to joining Cadence, he has worked in Xilinx and Ericsson.

Sorna Inian holds a Master’s degree in Electrical Engineering from the University of South Florida. She has been with Cadence Design Systems since January 2023, working as a Senior Application Engineer supporting the Jasper Formal Verification tool. She focuses on customer training and debugging formal issues. Outside of work, she enjoys music production. She is based in San Jose, California.

Sneha Gorantala joined Cadence in 2016 after receiving her Master’s degree in Electrical and Computer Engineering at Georgia Institute of Technology. Sneha is currently a Senior Principal Design Engineer in Cadence’s Tensilica DSP group. Over the last 9 years she has contributed to many DSP product lines including Vision, Audio, and RLC and has most recently led the microarchitecture design of Tensilica’s first accelerator, the Vision4DR. 

Shekhar Ubhe received his Bachelor of Engineering in Electronics and Telecommunications from Pune University and his Master of Business Administration from Symbiosis Institute of Business Management, Pune. He is currently a Design Engineering Director in the SSG TPG, where he focuses on Xtensa core verification and Functional Safety Design Verification. 

Shashank completed his B. Tech in Computer Science from NIT Srinagar in 2013. He has around 12 years of experience in Software Development ranging from OS development to EDA.

He joined Cadence 3.5 years ago and has been involved in the Power Reduction Technology in Joules.

He has developed various features in Reduction to improve the overall user experience of this technology. The features include writing the Reduction DB, rendering the HTML based reports, starting the GUI and runtime improvement in Reduction Algorithms and commands.

He has also enhanced the algorithms of Power Reduction to significantly improve the power numbers associated with the reduction algorithms.

He is working to bring LEC verification to Sequential Technology, which is gaining traction at customers.

He is a sport enthusiast and loves to play Cricket, etc.

Shakti Malik completed his B.Tech/M.Tech from IIT Kanpur in 2009 and has over 16 years of experience in the EDA industry. 

Shakti is working as Software Architect in Joules. He architected and developed a new simulation engine ‘FlashReplay’ with 10X-50X runtime improvement over existing Replay technologies. He also developed the Delay Simulator for Innovus GigaOpt Glitch power optimization and Graph Parallelization infrastructure Infra, which powers key algorithms in Joules Studio.

Earlier he was the owner of the Powermeter dynamic current construction engine in Voltus. He also worked on Spice Power correlation framework and ML assisted NLPM current modelling.

Shakti’s is passionate about Cars, Gadgets and Modern C++.

Shahin Golshan is an R&D software architect in San Jose, CA with 15 years of EDA experience in static timing analysis. His primary focus has been timing infrastructure for both Innovus and Tempus, especially runtime and performance improvements. Shahin earned his PhD degree in computer science from the University of California at Irvine. He started his career in 2011 as a senior software developer at Synopsys in Sunnyvale, CA then joined Cadence San Jose, CA in 2022.

Seungwon Kim is a Lead Software Engineer at Cadence since 2022, and formerly a postdoc researcher at UC San Diego’s VLSI CAD Lab under Prof. Andrew Kahng. He received his Ph.D. from UNIST in 2019 in South Korea. His research focuses on machine learning for physical design  detail routing, PPA-aware physical design methodology. He has been actively serving on the ACM/IEEE System-Level Interconnect (SLIP) workshop committee since 2020.

Scott Huss received the B.S. and M.S. degree in electrical engineering from North Carolina State University in 1989 and 1991 respectively.  Since 2011 he has been with Cadence in Cary, NC  architecting and designing high-speed circuits and systems for transceivers and die-to-die links.  He is the system architect for several Cadence PHY IP’s including the PCIE 6.0 product line.  He previously was with IBM and Maxim Integrated Products (now Analog Devices) designing circuits for communication, medical, and multimedia applications.

Saurabh Agarwal is a Software Architect at Cadence. He in DSG group and works on Genus, Innovus and Joules. His primary area of focus is low power implementation and optimization. He has been with Cadence for more than 15 years. He holds a Doctorate in Algorithms from University of Aarhus, Denmark and a Masters from Indian Institute of Technology, India. 

Salome Devkule has been with the Tensilica IP Group for the past four years, working on the design of the Xtensa processor. She will be presenting her paper, “Power Down! Memory Power Reduction Techniques for Low Power Design,” a topic that resonates with many working on power-conscious systems. In today’s world of battery-drained devices and increasing computational demands, her talk focuses on practical ways to make memory more energy-efficient without sacrificing performance. Outside of work, Salome enjoys traveling and exploring new places. She’s looking forward to sharing ideas, engaging in thoughtful discussions, and learning from fellow attendees.

Salome Devkule has been with the Tensilica IP Group for the past four years, working on the design of the Xtensa processor. She will be presenting her paper, “Power Down! Memory Power Reduction Techniques for Low Power Design,” a topic that resonates with many working on power-conscious systems. In today’s world of battery-drained devices and increasing computational demands, her talk focuses on practical ways to make memory more energy-efficient without sacrificing performance. Outside of work, Salome enjoys traveling and exploring new places. She’s looking forward to sharing ideas, engaging in thoughtful discussions, and learning from fellow attendees.

Salome Devkule has been with the Tensilica IP Group for the past four years, working on the design of the Xtensa processor. She will be presenting her paper, “Power Down! Memory Power Reduction Techniques for Low Power Design,” a topic that resonates with many working on power-conscious systems. In today’s world of battery-drained devices and increasing computational demands, her talk focuses on practical ways to make memory more energy-efficient without sacrificing performance. Outside of work, Salome enjoys traveling and exploring new places. She’s looking forward to sharing ideas, engaging in thoughtful discussions, and learning from fellow attendees.

Rodrigo Zeli is a Principal Design Engineer at Cadence with more than 12 years of experience working with ASIC design. He holds a B.Sc. in Computer Science from University of Sao Paulo in Brazil and coursed the Brazilian National IC Program. He is passionate about RTL design and optimization. Nowadays he is part of HSV ASIC Team and is directly involved in Cadence’s Next Emulation Platform development.

Regina Thahir joined Cadence in July 2024 after receiving her bachelor’s degree from UCLA in data theory (mathematics, statistics & data science). She is working as a software engineer in Sigrity R&D, where she implements her previous experience in mathematical modeling, statistical analysis, and machine learning to develop electromagnetic simulation software tools and optimize performance in systems design & analysis.

Ravi graduated from Florida State University with a master’s degree in Industrial Engineering in 2004 and has over 20 years of experience in leading multidisciplinary CAE simulation teams in the automotive industry. Currently, he serves as a Customer Service Engineering Director at Cadence. He joined Cadence through BETA CAE acquisition in 2024. At BETA, he leads a team of engineers in providing innovative CAE simulation solutions and workflows to customers across various industries. Ravi's expertise lies in morphing and multidisciplinary design analysis and optimization. Outside of work, he likes reading and hiking.

Raj Mitra is a Software Engineering Group Director at Cadence. Over 20 years he has contributed to various Cadence products, including Quantus QRC, Virtuoso physical design products and Virtuoso Analog Design Environment. He holds a PhD from Washington University in St. Louis, B.S. from Indian Institute of Technology and an MBA from Indian Institute of Management.  

Quang Le graduated from the University of Arkansas in 2022 with a Ph.D. degree in Electrical Engineering, specializing in design automation and optimization tools for power electronics modules. He joined Cadence in 2022 and is now a Lead Software Developer in the Analog-Mixed-Signal group. He is currently working on Analog-Mixed Signal features for Xcelium, Spectre, Simvision-MS, and Simvision Analog Debugger.

Qingyu Lin graduated from the Chinese Academy of Sciences with Ph.D. degree on Semiconductor and Micro-electronics in 2008. He joined Cadence after that and now is AMS Designer Product Engineering Director in Cadence. He owns 7 U.S. patents in the mixed-signal simulation and verification areas.

Prashant V. Agarwal joined Cadence Noida-India, in 2007, and works as a Software Architect in Virtual Protocol – HSV Protocol team.

At Cadence, he has worked in Palladium compile flows, Simulator Emulator Interface layers for Simulation acceleration, Emulator driven Functional and Code Coverage, and various performance improvement aspects. 

For last few years, he has focused on Hw-Sw co-verification - via Cadence Virtual Bridge product enabling the QEMU based Virtual Machines to connect and access 

with RTL running on Palladium. He has filed 4 patents during his work, and won awards at few Cadence Hackathons.

Prashant received his MS (BITS, Pilani) in 2007, and  BTech (CIT, Coimbatore) in 1997.

Paula Mathias is a Senior Principal Product Engineer at Cadence with more than 10 years of experience working with product development, project management and software quality. She holds an MBA in Data Science and Analytics from University of Sao Paulo in Brazil and is passionate about communication and interpersonal skills. She currently leads the product development of Generative AI applications in Jasper Formal Verification Platform.

Olivier Berger joined Cadence in 2005 (France Office). He has a MS in engineering and electronics from Polytech Montpellier school in 2004.

He has developed new functionalities for Virtuoso in Graphic Editor Team then joined Interactive Editing Team where he worked mainly into interactive routing functionalities (create wire, stretch, bus edition and usability, WSP snapping, coloring) and into electrical and simulation routing (SDR, auto connect). He also co-developed productivity and quality tools like cictest-review (quickest analysis) and crash explorer.

Since 2024 he has worked in design migration placement and routing.

Nicolas Delsate holds an applied mathematics degree from the University of Namur and a master's in Astronomy & Astrophysics from the University of Paris. He completed his PhD thesis in Celestial Mechanics at Namur. Joining Numeca in 2013, he transitioned to Cadence in 2021 after the acquisition of Numeca. Nicolas is now Software Engineering Director, heading the 'Unstructured mesh generation' group of Fidelity in Computational Fluid Dynamics. He developed algorithms like periodic matching meshes and automatic refinements. Nicolas actively contributes to brainstorming phases, including the initial AutoSeal development.

Niall Timlin-Canning has a BEng Electronic & Computer Engineering from University of Galway, Ireland.

From 2017 – 2022 he worked for CreVinn providing ASIC design & verification services, on projects including:

•    Switching Mode Power Supplies 

•    USB3.1 controller

•    NPU-SoC verification

Niall joined Cadence in 2022 as part of Cadence’s acquisition of CreVinn.

Since joining Cadence, he has worked on DDR controller designs including ASIL-B certified LPDDR5 Automotive memory controller, and DDR controller new AIQ architecture.

Morna Baillie is a Product Engineer for Celsius EC Solver - an electronics cooling simulation tool for accurate and fast analysis of the thermal performance of electronics systems using computational fluid dynamics. Based in Fort William, Scotland, she works with the Celsius EC and Reality DC teams, driving feature development and engaging with customers to provide support as well as translating requirements into future software features. 

Morna is a graduate of the University of Strathclyde in Glasgow, Scotland. She earned her Bachelor’s and Master’s degree in Mechanical Engineering, with a focus on computational dynamics and heat transfer. 

Mirlaine Crepalde has been working at Cadence since 2011, currently leading R&D for Jasper Hardware Description Language (HDL) compiler. Her focus is on evolving the technology to scale while maintaining its high quality. Holding a Master's degree in Computer Science from Federal University of Minas Gerais, specializing in formal verification, she continues to foster university collaborations, bridging academia and industry expertise.

Mike Kindig is an Application Engineer Architect based in Austin, Texas. Since 2015, he has supported customers in North America with Jasper formal verification. He graduated from Rochester Institute of Technology in 1994 with a degree in Electrical Engineering Technology. His career experience over 30 years has included PCB and FPGA/ASIC design and verification in Telecom, Networking and Satellite Communications industries.

In 2012, he began using Jasper to verify functionality in a Network Security processor and identified 30% of the critical bugs in connection tracking and FSM logic using Jasper alone. This led to his interest to work at Cadence to learn as much as possible about Jasper and use it full-time.

Mike was a recipient of the Cadence WFO High Performance Award in 2022 and was nominated for Cadence AE of the year in 2024.

Mike Prikhodko is a Senior Software Architect in the Virtuoso team based in San Jose. 

After earning his MS degree in mathematics at the Moscow State University he joined Cadence Moscow office in 2011, while teaching math to in the high school in his spare time. In 2017 he moved to San Jose office. During his tenure at Cadence, he worked on various Virtuoso infrastructure and flow projects, such as multi-patterning technology, silicon photonics, and heterogeneous integration. 

Matheus Henrique Bueno is a Lead Software Engineer at Cadence Design Systems, where he is a contributor to the Sage project for Verisium Debug since 2021. He holds a BS and MS degree from Minas Gerais Federal University (UFMG) in Electrical Engineering, focused on Power System. This foundation has equipped him with expertise in numerical techniques, algorithm design, model-based approaches, power transients and protection studies.

Mateus Silva is a Principal Software Engineer in Jasper R&D. Specialist in formal verification and low power solutions.

Mark has more than 30 years of experience at Cadence, spanning both analog and digital design as well as infrastructure. He is currently leading Agentic AI development for Virtuoso. Mark has a Bachelor of Science degree in Electrical Engineering and Computer Science from Rensselaer Polytechnic Institute and a Master’s degree in Computer Science from Stanford.

Mansi Mehrotra received the Bachelor of Engineering degree in Electronics Engineering from Indian Institute of Technology, Varanasi (IIT BHU), India, in 2012. With more than 11 years of experience in the digital design of Controllers and PHY Subsystems across various standards, she is presently a member of the high-speed Serdes group at Cadence Design Systems. In addition to her professional pursuits, she is also a mother to a 4-year-old, wife, and a sports enthusiast. 

Madan Kumar Nath received B. Tech degree in CS and M. Tech in Information Systems in 2001. He has been working in EDA industry since then. He has diversified experience in Digital Media, MPEG2,4, H.264, Web Technologies, CAD, Flow Automation, RTL Compiler, logic Synthesis, Emulation.  Co-author in 2 US patents.

Currently working as senior software engineer in HSV Protocol Team.

Maayan Ziv holds a BSc degree in computer science from the Jerusalem College of engineering, graduated in 2010. Maayan is working with Cadence for 15 years, started her way with Jasper just after graduation. During that time Maayan developed and led several applications of JasperGold, such as BPS, Superlint and CDC. Today Maayan is leading the development team of one of Verisium applications called WaveMiner, which aims to boost the debugging effort for our customers using innovative solutions.

Lixin Xu completed both his bachelor's and master's degrees in Integrated Circuit Design at Hefei University of Technology, with his master's studies focusing on power chip design. After graduating, he joined Cadence and has been working in the DSG PV team for six years. He began by delving into the Innovus database field and the CAT program. Later, he became one of the earliest pioneers in the product development of Cadence Integrity 3DIC. His primary responsibilities have included integrating Innovus and System Planner databases, designing basic user interaction interfaces, performing cross-product platform verification and release, and providing solutions and verification for TSMC's 3Dblox project. Recently, his interests have focused on Cadence's 3DIC high-performance full-flow solutions and the application of AI in the 3DIC area.

Laurent Saint-Marcel has 2 MS in software engineering and electronic from the Ecole des Mines de Paris. 

Since he joined Cadence more than 20 years ago, he has been working on many custom layout projects, mainly in Virtuoso, such as routing, connectivity extraction, electrical and simulation aware routing and migration. He enjoys developing internal tools to improve debugging and code stability. He is the co-author of the Weload debugger, Cictest-review and Crash Explorer. 

He is now Sr Software Architect and leads 2 Virtuoso teams working on design migration and automatic track generation for placement and routing.

Kushagra Gupta is a software engineer at Cadence, where he works on developing new applications for analog and mixed-signal design by combining his background in optimization and machine learning with the deep domain expertise of his colleagues. He joined Cadence in 2023 after completing a master’s in Statistics from Stanford University and a bachelor’s in Mathematics and Computing from the Indian Institute of Technology Kanpur. Kushagra is based in Seattle, Washington, where he reads far too much historical fiction, headbangs to heavy metal, and draws (slightly unscientific) dinosaur-themed comic strips outside work.

Kelvin McCollough received his B.S. in Comp Eng from University of Illinois and M.S. degree in Electrical Engineering from University of Missouri Columbia in 1986 and 1990 respectively.  Since 2017 he has been with Cadence in Cary, NC modelling high-speed circuits and systems for transceivers and die-to-die links. He previously was with Motorola and ViXS designing analog circuits for microcontrollers and digital multimedia applications.

Kei Wang has a MS in computer science from National Chiao-Tung University in Hsinchu Taiwan.

He worked in Cadence for 10 years. During the period, he has worked in interactive routing team to implement new features and support new DRD rules for the interactive routing part of Virtuoso. Now, he is working in the auto track generator for the APR and the layout migration project. He also likes to develop new tools that can be used in daily work to reduce develop time and validation time.

Kaushik Yanamandra is a Principal Design Engineer at Cadence, Cary with over 8 years of experience in High-Speed Serdes Design. He has contributed to the development of PCIe 6.0, Die-to-Die and Low-Power PHY IPs, with expertise in receiver and clock path circuits. Previously, at Texas Instruments, he worked on PCIe 3.0-5.0 retimer and redriver catalog products and led their verification and test efforts. Kaushik holds a B.E. in Electrical Engineering from BITS Pilani (India) and an M.S. in Electrical Engineering from NC State University. He is an inventor on 6 patents in the field of analog/mixed-signal design. 

Kang graduated from the Illinois Institute of Technology (Chicago) with a Ph.D. degree in Mechanical Engineering in 2015. He was with Siemens Corporate Technology (Princeton, NJ) and Siemens Teamcenter Visualization (Ames, IA), before he joined Cadence Sigrity - Beijing office in 2021. He is currently in the Sigrity Mesh team, leading the development of CAD geometry cleaning project, in close collaboration with several academic institutions dedicated to the state-of-the-art technology research on geometry modeling and processing.

Kanchan is a Product Engineer working with Cadence for the last 3 years. She has about 10 years of hands on EDA software development industry experience. 

She graduated with Bachelor’s degree from Pune University and Master’s degree in computer engineering from Missouri University of Science and Tech.

She has been involved in integrating system level tools with analysis tools for early performance testing. She has also been working on solving next generation SI challenges and providing customers solutions with fast turnaround time.

She is a mom of a 1.5-year-old and in the free time loves reading! 

Joshua Mathews holds a Bachelor’s in Computer Science from the University of Wisconsin – Madison and a Master’s in Computer Science from Carnegie Mellon University. 

He has been at Cadence for over 2 years, working as an R&D engineer in the Cell Infrastructure team for the parasitic extraction tool Quantus. He also works on the SPEF/DSPF comparison tool rccompare. He has implemented various features and optimizations for the tools, including enhancing the virtual metal fill flows and adding parallelization for the P2P resistance solvers.

Jonathan Zhang is Sr. Software Architect in Voltus R&D and is responsible for the development of Voltus-Insight AI product since he joined Cadence 4.5 years ago. Jonathan has 20+ years of experience and has held various roles in EDA, library design and physical implementation. His primary interests are in power integrity, low power design and overall design closure. 

John DeFord attended the University of Utah where he received B.S. degrees in physics and mathematics, and M.S. and Ph.D. degrees in electrical engineering.  After graduating in 1986 he worked at Lawrence Livermore National Laboratory (LLNL) for 7 years, where he developed time-domain electromagnetic codes for modeling particle accelerator components, as well as managed research into numerical methods for EM simulation.  After leaving LLNL Dr. DeFord joined MacNeal-Schwendler (MSC) where worked in the Electromagnetics Branch for 3 years as the Product Manager for their finite-element EM modeling software.  This group was sold to Ansoft in 1997 in their first acquisition as a public company, where he worked briefly before founding Simulation Technology & Applied Research (STAAR).  STAAR developed the Analyst code and worked on a variety of SBIR projects, primarily funded by the Department of Energy.  STAAR was acquired in 2008 by Applied Wave Research (AWR), after which he focused on finite-element solver enhancements needed in Analyst for use by AWR customers. Since AWR was acquired by Cadence in 2020 Dr. DeFord has primarily worked on Clarity feature development.

Huan-Ting (Joe) Meng received the BS, MS and PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign in 2008, 2011 and 2015, respectively, where he researched on Computational Electromagnetics time-domain algorithms, GPU acceleration, and large-scale parallelization.  He is currently a Sr. Principal Software Engineer in Quantus Extraction Solution, developing advanced technology node enablements and novel capacitance modeling methodologies.

Jiyue Zhu got his Ph.D degree of electrical engineering from University of Michigan at 2021. He is working as an R&D at the Sigrity team, MSA, CPG. His works focus on AI models for solutions of signal integrity and power integrity for the PCB and chip design. He also creates solutions for 3D simulations in DC solvers.

Jens came to Cadence the first time in 1997, after having earned his University diploma (“Dipl.-Ing.”, equiv. of Masters degree) in Electrical Engineering from the Technical University of Berlin. He had worked in different Methodology Services and Application Engineering roles at Cadence Germany until 2017, as a contributor, team Manager and AMS Solution Competency lead for Cadence’s full-custom IC and simulation products. From 2017 until 2023 Jens was a Product Engineer and PE Manager at Mentor Graphics/Siemens EDA, for their Mixed-Signal simulation products and flows. 

Since end of 2023 Jens holds a Product Engineering Architect role back at Cadence Germany for the Automotive solution within the CPG business unit. One of the focal technical topics has been the Functional Safety verification flow and methodology to be deployed by customers on Analog/Mixed-Signal designs as part of their Automotive ISO 26262 product certification process. 

Jason Potnick is the Texas DSG AE Director, based in Dallas, TX.  His team supports Cadence digital tools for a wide variety of GEO customers throughout Texas.  

Jason attended UC Berkeley and joined Cadence in 2013 as an AE after a 10-year career in ASIC design.  

A father of six, Jason enjoys spending time with his family, coaching youth sports, staying fit, and watching movies.

Janez Jaklic is a Senior Software Architect in the Virtuoso Infrastructure team based in Germany.

After earning his Diploma degree and PhD in theoretical physics at the University of Ljubljana he joined Cadence in 1997 and worked for over 20 years as Application Engineer and later Application Engineering Director supporting physical verification, custom IC, IC packaging and board design platforms of Cadence. Since 2018 he is a member of Virtuoso R&D focusing mainly on the infrastructure for curvilinear layout design and verification.

Jaise P Raju is a Sr Principal Design Engineer on the DDR Design IP Firmware Development team. He has been with Cadence since 2013 and holds a Bachelor of Engineering degree in Electronics and Communication from Visvesvaraya Technological University in India. Prior to his current role, Jaise worked on silicon validation and customer support within the DDR PHY IP team.

Igor Murta is a Software Engineering Manager who has been working with the Cadence VFS team for the past decade. During his trajectory he was part of the Jasper PV team, working on validating this formal tool, and later on he moved to manage the VFS DevOps team, developing tools and solutions to improve R&D productivity.

Igor is now working on the VIP product, leading VIP Brazil site and managing Quality Assurance and FTT Software Development teams.

Hanqi Yang joined Cadence in 2018 after earning his M.S. in Electronic Science and Technology from Southeast University. Currently a Principal Product Engineer in the Digital & Signoff Group (DSG), he specializes in prototyping, early hierarchical floorplan synthesis, and 3D-IC design methodologies. Hanqi has secured two patents in 3D-IC technology, driving innovation in advanced-node physical design and heterogeneous integration.

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Shuaeb Fazeel received the B.E degree in electronics and communication engineering from the College of Engineering, Anna University, Chennai, India, in 2005, and the M.E degree in microelectronics from Indian Institute of Science, Bangalore, India, in 2007. From 2007 to 2010, he worked on high-speed transceiver circuits for memory interfaces with Rambus, Bangalore, India. From 2011 to 2016, he worked on high-performance data convertors in high performance analog group of Texas Instruments, Bangalore. From 2016 he has been working on high-speed memory interfaces in Cadence Design systems as a design engineering architect. He holds 21 granted and filed patents and has 4 IEEE published papers.

Guy Wolfovitz is a Senior Software Architect at Cadence Design Systems. Since joining the Jasper engines team in 2012, Guy has been involved in a range of R&D projects focused on hardware model checking technologies. Before joining Cadence, Guy was a postdoctoral researcher in the mathematics and computer science departments at the Hebrew University of Jerusalem, where he focused on probabilistic combinatorics. He holds a PhD in computer science from the University of Haifa.

Fortino Garcia joined the R&D division at Cadence in August of 2024 as part of the Allegro X AI team. Fortino works on applying optimization and machine learning techniques to automated PCB design, especially for automatic placement and layer assignment of components. Fortino obtained his PhD in Applied Mathematics from the University of Colorado at Boulder in 2021, and prior to joining Cadence was a postdoctoral researcher in the math department at New York University working on nonlinear optimization of physically constrained systems. 

Felipe Bordoni Diniz joined Cadence in January 2023, as part of the Jasper’s Quality Assurance team. He graduated in Electrical Engineering and had past experience in software development for Virtual Reality applications and in Electromagnetic Compatibility testing. Felipe works mainly validating Jasper HDL compilation features, OS support and implementing approaches for testing automation.

Fábio Teller Alves joined Cadence in 2022, as part of the Jasper Platform Debug R&D team. With long experience in scientific software development and machine learning, he has found exciting new challenges in working with product development. The presented poster is the fruit of a great opportunity to reconcile his past experiences with Jasper.

Vangelis Palaiokastritis earned his Diploma of Engineering from the Mechanical and Aeronautical Engineering department of the University of Patras in Greece in 2015.

He joined BETA CAE Systems in 2017 and currently serves as a Lead Customer Service Engineer at BETA CAE R&D Greece. 

In his role, he supports customers with the company’s software products ANSA pre and META post-processor, specializing in the fields of Composites, Material Modelling, Durability, and Fatigue Analyses. Additionally, he collaborates with developers to enhance the suite’s products and contributes to the R&D for FATIQ software.

Emmanuel Hagan is a highly innovative Analog Design Engineer with a strong commitment to precision and advancements in semiconductor technology. Since joining Cadence Design Systems in 2014, he been instrumental in designing high-performance Serdes, collaborating with cross-functional teams to bring advanced IC designs to fruition. He holds a Master’s Degree in Electrical Engineering from North Carolina State University. His successful transition from academia to Cadence is underscored by his technical expertise and exceptional problem-solving abilities 

Dirk holds an aerospace engineering degree from the University of Stuttgart, Germany, and a doctorate from the Institut National Polytechnique in Toulouse, France. He joined Numeca in 2010, where he led various R&D activities, particularly in uncertainty quantification and design optimization. He joined Cadence with the acquisition of Numeca in 2021. Dirk is a Software Engineering Director in charge of Artificial Intelligence research activities and AI application development in the field of Computational Fluid Dynamics (CFD). Based in Brussels, Belgium, Dirk enjoys running, gardening, and traveling in his free time.

Cristopher Villegas is an Industrial PhD. Candidate at Cadence’s Munich Office in Germany in cooperation with Ulm University in Baden-Wuerttemberg, Germany. He joined Cadence in December 2019 to the former System-design enablement Team (now part of the FAST team). He is also a former SoC Design Engineer from NXP Semiconductors, working for over 5 years at the Campinas site in São Paulo, Brazil. He has wide experience in the SoC front-end design flow, Verification, Virtual Prototyping, and, ultimately, Safety-critical SoC design. In the past, he published diverse papers related to these topics. 

I joined Cadence in September as a full-time employee. Before that, I did a 6-month internship at Candence, in the same team. During this internship I worked on a research project which was about using Deep Learning (Image processing) models on Analog layouts. I am now working on a layout migration project, based on heuristics rather than ML approach. I worked on a few side projects recently, the main one being the implementation of a VsCode extension for debugging SKILL language.

Mr. Christopher Tseng is the Director of System Software Engineering at HSV and spearheads a team of highly talented engineers for integrating the legendary Palladium emulators.  Christopher himself is a veteran engineer with a heart full of passions about the world of technology.  He started his career as a research engineer in signal processing but later being converted to a device-level software engineer accidentally.  The greatest pleasure of his is working alongside with all the brilliant minds around him and making innovative, solid, and scalable solutions. He is a strong advocate for GNU Linux, Free Software movement and culinary arts. 

Chirayu Amin is a Sr. Software Architect in Advanced Modeling and Analysis team of DSG. Chirayu works on modeling for timing analysis and cell library characterization. Chirayu has 20 years of industry experience in EDA for digital and analog circuit analysis. He holds a PhD in ECE from Northwestern University. At Cadence, Chirayu’s recent contributions have advanced the state of the art for design robustness analysis in design optimization and timing.

Chee Fang Ng, also known as Sandy is a Sr Principal Application Engineer in DSG North America. She is located in Santa Barbara, CA.

She joined Cadence back in 2022. With over 18 years of experience in digital SOC design and RTL-to-GDS signoff, she is passionate in developing flow and methodology to improve design PPA and TAT. She has helped numerous accounts and customers in low power synthesis solutions using Cadence Cerebrus, Genus and Joules. Today, she will share her novel approach to provide differentiated PPA to customers with early access program which also provide valuable feedback to the enhancement of Cadence Synthesis Solutions.

Bishnupriya Bhattacharya is Sr. Architect in Genus R&D at Cadence, Bangalore. She leads a team on logic synthesis high level optimizations.  

Throughout her career of 25+ years in EDA, Bishnupriya has been a technology leader in the EDA industry in the areas of synthesis, verification, simulation, and virtual prototyping. She has been actively associated with IEEE standardization committees and has made significant contributions to IEEE language standards including SystemC, and Portable Stimulus.  

Bishnupriya has published in prestigious peer-reviewed conferences and serves regularly in their Technical Program Committees and Steering Committees. She has been granted multiple US patents and has also co-authored a book on UVM Mixed Language. She currently serves in the Cadence Patent Committee.  

Bishnupriya has obtained her B. Tech in Computer Science from Jadavpur University, India, and her MS in Electrical Engineering from University of Maryland, College Park, USA. 

Arvind Veeravalli is a Senior Architect in Tempus Product Engineering Team. He works on developing Big design and 3dIC signoff solutions in Tempus. He also works closely with multiple customers like Broadcom, Renesas, Socionext to enable successful adoption of Big design solutions. He has authored over 25 external papers and holds 6 patents. Prior to joining Cadence, he worked as Chief Technologist for EDA solutions in Texas Instruments.

Artemii Sattarov is a Product Engineering Manager at Cadence working on Computational Fluid Dynamics (CFD) and Computer-aided Engineering technologies. He concentrates on Aerospace and Defense applications. Artemii holds a BSc in Aerospace Engineering and an MSc in Computational Mechanics. His Erasmus Master’s studies were held at UPC BarcelonaTech and Swansea University. He joined Cadence with the acquisition of Numeca in 2021. Prior to joining Numeca in 2017, he worked on several research initiatives at ANTONOV and the Barcelona Supercomputing Center. 

Arnab Bhaduri is a Distinguished Engineer in the SSG Tensilica team, where he leads the platform software team working on Xtensa and Swerv tools, firmware and OS support. The platform software team is responsible for all debug support, including third-party and open-source debug tools and Palladium/Protium based debug. Arnab is also involved in functional safety and security related initiatives within Tensilica. He has been at Cadence for more than ten years, helping deliver multiple generations of Xtensa hardware and software.

Angelina Silver holds a BSc degree in computer science from the Tel-Aviv University. Angelina is working with Cadence for 6 years and has over 25 years of design and development experience. Angelina joined Perspec group and since then leads the Language team which is responsible for compiling PSS files. Angelina also serves as the Cadence representative in Accellera Portable Stimulus Working Group, contributing to development of PSS language and methodology standard.

Amy Lim is a senior architect on the software team of the Palladium products in SVG. She received her Ph.D. in CS from Stanford University and her M.S. in EECS from MIT. She joined Cadence in 2005 and has been involved in developing advanced technologies and methodologies that deliver high-performance acceleration on the Palladium platforms. Her work focuses on behavioral modeling and advanced transformation. She is currently working on emulation solutions to support behavioral assertions, delay modeling, and real number modeling (RNM) in DMS designs. Based in San Jose, Amy enjoys dancing, craft-making and puzzle solving in her free time.

Amit is working at Cadence in Pune, India as a Design Engineering Director in SSG TPG DSP Vision group. Amit is signal processing lover with 26+ years of experience in audio, image and vision algorithms. For past few years, worked on development of Visual SLAM (Simultaneous Location And Mapping), Point Cloud Library and Radar SLAM related applications and their highly optimized implementation on world class Cadence® Vision DSPs. Ranked first in Pune University when completed Bachelor’s degree in Electronics & Telecommunications. Received most outstanding student award when completed Master’s degree in Communication Engineering from Indian Institute of Technology, Bombay. Holds US patent for new method for comfort noise generation. Winner of best paper presentation for CIC India 2023 for inventing new method for accurate stereo rectification of images. 

Amir Ben-Avi is IT Architect, that part of the IT Cloud/DIT team in Cadence.

Amir has been with Cadence for over the last 8 years and had 25 years of experience in the Information Technology field and in the Semiconductor industry, previously worked at Marvell & Freescale Semiconductor (NXP).

Amir holds a B.A in Computer Science and very passionate about new technologies as well driving innovation and efficiency in every part of the work.

He actively serving in Cadence as an SME for the areas: LSF, Slurm and Container and supporting various groups within SVG R&D.

Amir is place in IL site, and is one of the IL IT leaders 

Amin Farshidi joined Cadence in 2016 after receiving his PhD in Electrical and Computer Engineering from the University of Calgary in Canada. Amin is currently an R&D manager at the DSG’s Innovus CTS team specializing in power-aware clock tree synthesis and latency optimization for timing closure. He has been a project lead in accomplishing major projects such as activity driven CTS V1/V2 and improve insertion delay/skew which significantly enhanced the tool’s out-of-the-box performance as well as major high performance customer specific features such as tight clock tree recipe and insertion delay driven CTS flow. During his tenure at Cadence, Amin has had 7 patents and 3 trade secrets.

Aman Kumar joined Cadence in 2017 in RnD, after completing B.Tech. in Computer Science from Delhi Technological University.

In Genus, he works on commit power intent. Developed port-splitting to resolve RTL bottlenecks and produce better PI netlist. Developed check_power_intent to do LP checks in Genus itself for LP verification, reducing TAT. In collaboration with DFT team, DFT SDA flow, an integrated solution to produce better PI-aware netlist post-dft. 

In Joules-Studio, co-developed analyze_timing to categorize worst timing paths, providing insight to fix early in RTL. He co-developed RTL-Restructuring feature, to provide more flexibility to designers for SDC & UPF aware RTL manipulations.

Alex Passi joined Cadence in 2014 as an engineer in MIPI Verification IP team. During his career in Cadence, Alex led development of AMBA Verification IPs family, as well as development of several System Verification IP products: System Verification Scoreboard, System Testbench Generator and System Performance Analyzer. Now Alex works in Foundation Technologies Team of Verification IP Group and leads VIP AI Core Team, coordinates AI projects in VIP Group. 

Alan is a software engineer who works in the USF backend of our Midas Functional Safety Platform. The USF is written in Tcl, a language which conquered a place in his heart. In his daily work, following a "chaotic good" alignment, he tries to keep the fine line between order and chaos for exploring the disruptive while respecting the elders, thus hoping innovation.

Akshay Rawat is a Principal Product Engineer at Cadence Design Systems, specializing in the physical verification specifically focusing on Layout Versus Schematic (LVS) verification. He holds a Master of Science degree in Electrical and Electronics Engineering from California State University (2013)

For the past seven years, Akshay has been a key contributor at Cadence, dedicating the last five to the advancement of 3DIC technology. His current role centers on the seamless integration of Pegasus 3DIC with planner tools such as Integrity, Virtuoso and OrbitIO while also engaged in Indesign flow enablement.

Beyond his professional achievements, Akshay enjoys a diverse range of interests, including cooking, music composition, travel, and gaming.

Dr Adronis Niyonkuru is a Sr Software Engineering Manager leading an R&D team based in the United Kingdom and working on Virtuoso Analog Design Environment (ADE). Adronis first joined Cadence in 2012 as Sr Software Engineer and stayed with the Virtuoso Layout XL team in the UK for 7 years. He rejoined Cadence in 2022 and moved since then into R&D management.

With his wide-ranging technical background earned during his career as software developer for over 15 years, Adronis supports the wider Virtuoso ADE team in development and deployment of large-scale cloud solutions which allow customers to run analog design simulations in parallel on various platforms. Those solutions include highly customizable interactive run modes, and intensive simulations performed in batch mode with a smart scheduling capability. 

Adronis received a PhD degree from the Helmut-Schmidt University in Hamburg, Germany.

 In his free time, Adronis enjoys playing basketball, long walks, reading books and listening to music.

Adarsh Pandey completed his B.Tech in Electrical Engineering with a specialization in Computer Science from Dayalbagh Educational Institute in 2022. He has been with Cadence for 3 years, where he works in the Placement and Routing Optimization team. His contributions focus on enhancing the timing, area, and power efficiency of Innovus, a leading digital implementation tool.

Adarsh has worked on improving node resizing algorithms, implementing effective library cell pruning techniques for runtime improvements and scalability enhancements. He has also been actively involved in power-driven optimization strategies for advanced chip designs.

Christophe Fouassier received his master in Electronic in 1998 from the university UPMC of Paris, France. He entered Mentor Graphic and worked in the emulator area. Then he has joined Cadence for more than 25 years. Its main projects are interactive and assisted routing. He is now more focused on the Virtuoso migration project, working on placement and automatic routing. Christophe is the author or co-author of 3 patents, still in the routing area.

Peter Herth is one of the developers of the Cadence PCell Designer. He joined Cadence in 2005 as a Services AE and worked many years as a Services Engineer until the PCell Designer became the main project. He holds a Masters in Physics from the University at Cologne, Germany. 

Stephen Allott has a B.Eng. Hons and a Ph.D. in microelectronics from the University of Huddersfield, England. He has approximately 30 years of experience in the semiconductor industry.

Stephen joined Cadence 2 years ago and works as a Sr. Principal Applications Engineer in San Jose. His primary focus is on front end tools to enable RF and microwave design. Before joining Cadence, he worked in semiconductor design, mainly focused on the cellular space. His previous experience also includes work on multiple cellular standards from IS-95 to LTE and 5G. He also worked on wireless products in the non-licensed bands such as Bluetooth, WifFi, and UWB. He developed this experience working in such companies as Qorvo, Microchip, Renesas, GlobalFoundries and Marki Microwave. Today he is applying this knowledge to develop flows that meet the needs of tier 1 companies that are aiming to produce  highly integrated solutions that operate at frequencies commensurate with the microwave space.

Lovejeet Singh is an IT Staff Enterprise Developer and has been with Cadence for 9 years. Currently based out of Cadence Ireland, He has a Bachelor’s Degree in electronics from NIT Jalandhar in India. In Cadence, Lovejeet works in several IT applications that help the business, focusing on innovation and increasing the productivity. He has been on an architect role in RPA bringing innovation to the automation area. Along with his team he has automated several IT and Finance processes in RPA saving hundreds of hours by automating the repetitive processes.

Simon earned a PhD in Mechanical Engineering from VUB University in Brussels. His work focuses on bridging the gap between simulation tools and the physical world by incorporating parameter statistical variability. He started his career in the CFD domain before transitioning to the EDA industry. Currently, he works on Statistical On-Chip Variation (SOCV) modelling in Tempus, where he helps improve timing signoff accuracy. Simon is also actively involved in achieving certification with leading foundries such as TSMC and Samsung, in order to support advanced technology nodes.