Presenter Portal

Companies are producing advanced chips with enhanced computational power for AI/ML applications. However, these chips face significant challenge due to high power consumption. To address our customer needs, it is essential to shift the optimization focus solely from timing to power efficiency also. This presentation will explore opportunities to enhance the optimization flow for better power consumption while maintaining the timing accuracy.

We describe new pre-route estimation tool which is based on the current global router engine.

The presentation discusses an effective method for profiling and analyzing performance issues in distributed applications. It involves collecting raw data in Common Trace Format (CTF) and using open-source tools like Babeltrace and Trace Compass to post-process the data. This approach helps identify performance bottlenecks through various visualizations such as graphs, charts, and tables. Additionally, it showcases how the Liberate Team has successfully utilized this method to pinpoint and resolve performance bottlenecks.

3DIC designs integrates dies such as logic, memory, analog, RF, and MEMS. Heterogenous integration allows system designers to use die with different technology process nodes. As we add more-and-more dieâ s on to 3D-IC, it poses a greater challenge for Physical Verification tools to run DRC, LVS and Antenna checks. In this presentation we will cover Pegasus 3DIC System-LVS flow which let users run DRC, ERC, LVS, and Antenna checks across the whole 3D structures. The LVS flow here does not need a rule deck and can check the whole connectivity of the 3D system.

Checking of curvature design rules and representation of polygons by curvilinear shapes requires extraction of curvatures from manufacturing data. We show that curvatures obtained by direct numerical differentiation of polygon edge angles are inherently inaccurate due to the noise caused by the random snapping of polygon vertices to the manufacturing grid. We present a method to obtain much more accurate curvature values indirectly as the solution of an inverse problem like in Tikhonov regularization that is denoised using the method of total variation regularization. The resulting extracted curvatures are sufficiently accurate for design rule checking while still exhibiting discontinuities.

The purpose of this presentation is to showcase the capabilities of ITs first GenAI enabled chatbot 'Newton' and how it is helpful for our users by answering IT specific queries and enabling various automations. Presentation also explains the need for Chatbot in IT because we want to serve our Customers. For us in IT, our internal users are our customers.We want to be more proactive and productive for our users. Newton has been trained specifically in IT applications related queries for example Outlook, Windows, MAC, VMs, Teams, Zoom, Zentera etc along with several automations like Setup Outlook on mobile etc..

This is a unique, innovative, and proactive solution desinged to increase the farm productivity by reducing the turn around time for server reimageing. This is a novel RPA solution in the indusrty which is proactively analysing the demand of the OS and predicting the Demand Trends. It plans the avilabability of different OS versions in future based on the demand trends of the past job submissions. We have seen a drop of upto 80% in the Turn-around time when compared to the manual process.

Improving EDA designers productivity is the key to surpass competition. â This presentation introduces the Virtuoso Turbo Bus Routing solution which is part of the next Virtuoso AI release and that was developed in partnership with Samsung, ST and Qualcomm.â Multiple innovative routing strategies were added to Virtuoso including reinforcement learning technics to automatically propose the best tool settings and use the most efficient algorithm according to the routing context.â Thanks to the new algorithms and use models, layouters now save around 60% of routing time on custom designs and Virtuoso displaced competitionâ s tools.â

FlashReplay is Joules new replay/simulation engine, written from scratch with a focus on parallelization and performance. It is already being used by multiple customers and has demonstrated a 10X to 100X runtime gain over existing replay technology. It has built-in glitch detection/analysis capabilities. It can also perform incremental simulations, allowing the optimization engine to simulate only the relevant parts of the netlist. FlashReplayâ s cell-level simulator can simulate 25 million toggles/second per thread. It is exported as a kit powering Innovus GigaOpt Glitch power optimization. A complete FlashReplay kit is planned to allow code-level integration into Innovus/Genus. Binary-level integration already available.

The presentation talks about some of the prominent challenges with modern designs optimization flow and how new generation tool 'Certus Closure Solution" infrastructure has managed to navigate through these challenges at technical and user level both. It will be of interest to R&D across tools and flows as well as PE and field teams also to be audience to this presentation and get to go through these challenges and how these are addressed and helped Certus to .be a industry wide differentiated solution.

Formal Verification (FV) is probably the most powerful validation technique available to users for verifying correctness of an RTL design. However, since it solves inherently hard problems on a routine basis, users face a bewildering selection of tool settings, knobs, and heuristics to chose from when configuring an FV run. In recent years we realized that there are a number of common techniques we recommend for setting up FV runs, based on a hierarchy of effort: using this insight, we enable users to efficiently run FV with optimal default behavior, using our "ProofMaster" framework.

Cadence VirtualBridge© is a HW-SW co-development, co-verification system. It involves multiple decoupled tools across network. VirtualBridge© involves Palladium/Xcelium, Proprietary communication channels, VM (Virtual Machine). It also involves network sockets, events, channel queues and threads. Some tools have localized save and restore, but unaware whole setup. Others, like sockets, events, threads do not have save/restore notion. Maintaining Coherency and reinstating network connections is challenging. This paper presents a innovate approach to coherently save and restore VirtualBridge© + Palladium along with other decoupled systems. Also included, a customer case study with 4+ Hours saving per developer per session.

Observability Don't Care(ODC) based sequential clock gating solution in Joules Standalone. Apply ODC based solution in genus to improve PPA. Provide conformal verification with LEC to verify sequential changes both in Joules Standalone and Genus. Good power saving achieved. LEC Verification completely verifies the changes and runtime is significantly better than other conformal tools.

Nonlinear n-port resistors or controlled sources having nonlinear characteristics are fundamental for nonlinear circuit synthesis. Creating multi-dimensional piecewise linear models of such nonlinear device characteristics aids in circuit synthesis and speeds up the analysis of such circuits using piecewise linear simulation. To create such PWL models, in this solution we are using an ML based method called Linear Trees. Linear Trees are an effective variation of the Decision Tree algorithm wherein at the nodes of the decision tree linear models of the form ax+b are fitted. The leaf nodes provide the PWL models and paths to them give the boundaries.

In this paper, we introduced the flow and solution to First 3DIC MoL (Memory-on-Logic) Tape-out in China using Integrity 3D-IC Platform. The flow and new technologies introduced in this paper include: concurrent implementation for multiple dies of 3D-IC, Pseudo-3D Timing Closure flow for multi-die concurrent optimization and timing closure, 3DIC clock tree structure, 3DIC RC extraction, STA and timing ECO; 3DIC Thermal/IR-drop/System-LVS/LEC signoff. With the flow and new technologies above, we finished Chinese First MoL (Memory-on-Logic) Tape-out.

SABER, a novel AI-powered debugger, uses Large Language Models (LLMs) like GPT-4 to automate static timing analysis (STA) debugging. Its multi-agent architecture mimics expert engineers, employing Tree-of-Thought reasoning and meta-concepts to identify violation root causes. Case studies demonstrate SABER's effectiveness in real-world designs, accelerating the debugging process and potentially reducing time-to-market. Future development includes incorporating multimodal LLMs for enhanced visual analysis.

Users of Jasper can benefit from RAG-LLMâ s through the use of automated abstraction and overconstraint mining. RAG-LLMâ s have recently shown remarkable capabilities in creating and analyzing code across various programming languages. We can leverage the strengths of RAG-LLMâ s to expose potential candidates for formal abstraction and overconstraints that are likely to improve results. A correct full proof on an assertion can be obtained with an imprecise abstraction and a correct counterexample trace for an assertion can be obtained with an imprecise overconstraint. This allows RAG-LLMâ s to be â creativeâ and imprecise while providing value as part of an automated formal flow.

The most advanced process nodes have more and more tough design margins related to RC parasitic effects. Hybrid (2.5D+3D) digital parasitic extraction flow addresses this problem reducing accuracy margins of parasitic extraction for full chip extraction. Enabling 3D-level accuracy for full chip extraction isn't trivial task, there are puzzles to solves starting from design preparation and partitioning down to results stitching, goes deep into engines enhancements. New flow is not simple sum of independent of 2.5D and 3D extraction, it is synergy of two.

FLIT Mode was introduced in PCIe 6.0 specification as a new data stream mode. The Flit Encoder (FE) is a complex and timing critical module in Data Link Layer (DLL). It has both control path and data path logic. It fills the TLP bytes in the flit by following rules mentioned in Spec.â In general, Formal Verification (FV) is effective in control paths but challenging for data paths due to large state space. However, applying the right approach can still find bugs if present in data path designs.â We present our novel data integrity ACT methodology to overcome verification challenges.

The presentation summarizes the work carried out in the last years to enable compatibility between Fidelity Pointwise meshes and density-based solver (DBS). Competitive accuracy, speed, and robustness properties of the new simulation workflow have been confirmed in a number of standard cases. Compatibility has also been extended to the output-based adaptive remeshing workflow. The new workflows are particularly suitable for Aerospace and Defense cases. Several A&D test cases, including the sonic boom prediction validation case, are presented to demonstrate these new functionalities.

As we are consciously evolving for sustainable growth and march towards building low power IC design, so is Stratus HLS building various method in its arsenal to help designers build energy efficient designs that can be controlled at a higher level. With the automation of the new power shutoff feature we can provide a list of minimum registers that designers can retain when power is shutoff thereby decreasing the leakage power which was traditionally done manually by designers that is time consuming or sometimes by retaining all the registers that led to increase in leakage power.

The drive towards zero prototypes and accelerating technological advances make it necessary for the CAE analysts to be able to rapidly set up complex morphing parameters to carry out structural performance optimization for ever-evolving designs. These complex parameters are beyond simplistic changes and need sophisticated integration of software capabilities and automation to carry them out. In order to effectively address these issues, this paper presents a framework for creating rapid parametric optimization setup using ANSA and Python scripting automation. The concept and the automated parametrization process are illustrated using a benchmark study carried out in collaboration with General Motors.

The presentation discusses area and feature enhancements to previously implemented Hybrid Phase Interpolator architecture with a focus on PAM-4 ADC based Receivers. This design is implemented in a TSMC-3nm process node accommodating datarates from 1Gb/s-64Gb/s with PI clocks operating at 4-8GHz. A new 8-phase PI encoding scheme that reduces analog routing and digital PD complexity is utilized in this design. A unified eye-surf mixer is implemented, that negates the need for a separate eye-surf path in edge-based CDR. It also has a unique capability to generate a frequency offset to test phase interpolator settings in a production environment loopback test.

In this paper we present a new solution for enabling electro-magnetic analysis (using EMX and Clarity) in both single IC and stacked ICs. In case of the single IC, this solution integrates with existing Virtuoso-Quantus post layout analysis flow; enables flexible selection of the parts of the design analyzed by the electro-magnetic solver based on the LVS extraction result; and provides automatic stitching of the results of the electro-magnetic simulation into the results of Quantus extraction. For the stacked ICs, this solution enables the simulation of the high-frequency signals crossing multiple dies with automatic stitching of the results into system schematic.

Finding issues in designs can be challenging due to the complexity of the problem. Usually debugging is done by analyzing a waveform. This step is complex and time-consuming as it includes a huge number of signals and cycles. According to Wilson Research Group, Verification Engineers spend approximately 41% of their time debugging issues in their design. This new tool introduces a flow that leverages LLM models to enhance the user experience and accelerate the debugging process. It is based on SVA properties and waveforms, making it suitable for formal verification, simulation and other tools that contain properties and/or waveforms.

In an era of rapid advancements in Artificial Intelligence (AI) and large language models (LLMs), waiting for a perfect solution means forgoing immediate advantages. This presentation emphasizes the need to adopt and refine current AI technologies to remain innovators. Introducing the EZ Agent framework, designed to empower teams to experiment and prototype rapidly. The framework facilitates the seamless incorporation of cutting-edge AI technologies into our products and promotes cross-team collaboration. The system enhances efficiency by allowing tool reuse and facilitating real-time data access. It optimizes workflows through a built-in orchestrator that manages dependencies and parallel processing.

In this submission, we exhibit our high frequency 3/5nm designs modelling the MIS margins using Tempus Adv-MIS (AMIS) & further we compare this approach with the other traditional methods. Around 100K paths were studied to see the slack distribution of SSI2 compared with AMIS & we observed the AMIS showed a realistic derating depending on the input arrival to output transition. We have qualified this methodology by validating the delay computed using Tempus AMIS with spice showcasing healthy correlation. Various enhancements were done in the tool to improve the verbosity & user experience for this feature.

We propose a Functional Safety methodology for early-stage estimation of the Diagnostic Coverage (DC), enabling efficient Safety Mechanisms development and its Design Space Exploration (DSE), and the discovery of Failure Modes through Colored Petri Net (CPN) simulations. To the best of our knowledge, the proposed work is the first DC estimation approach based on high-level models such as CPN. The methodology was verified in an automotive SoC, showing an average estimation accuracy of 97.2% and a 175x speed-up for a Software Test Library (STL) compared to results obtained through an exhaustive RTL FI campaign.

Signals crossing clock domains have caused many problems in designs across Cadence. This has led to customer-reported issues and associated perception of quality, many support engineering hours, and repeated re-issue of IP One culprit is our Async FIFO designed many years ago and used everywhere Recent advances in customer tools highlighted two significant issues: o Susceptibility to data corruption caused by potential glitches o Inability to handle large delay differences between nets crossing clock domains A robust Async FIFO, immune to both issues, is described here, using a number of innovative techniques: o Per-entry direct source to destination register transfers with handshaking o Multi-bit â validâ processing to eliminate Gray-code synchronisation

Time synchronization in routers is a crucial part of successful operation Achieving convergence (time sync) requires thousands of handshakes (~16ms simulation time) Often, multiple experiments needs to be run to decide on the best configurations for achieving convergence In this paper we present a novel predictive approach to identify the values of key parameters that predict the convergence trend without running the simulation for longer duration. This approach can be used for verification of time sync process of design This approach can also predict the time taken by router to achieve convergence with different filter strengths and on different modes by running single simulation

Electromagnetic (EM) solvers like Clarity provides powerful capabilities of characterizing the EM behavior of passive structures whether on board, package or IC. However, getting agreement between measurement and extraction is a non-trivial matter with many pitfalls both related to setting up the geometry, choosing solver and meshing settings as well as understanding issues that could come from the fabrication or measurement side. Attending this talk will help you interacting with customers around topics of comparison with measurements or customers who blindly trusts their existing tooling whether EDA, lab equipment or datasheets. The learnings could also help increase customer productivity.

A solution that can be attached to frontend Cadence tools and gives users an HDL design error root cause analysis, present explanations based on Verilog HDL Language Reference Manual standard and provides code snippet solutions to be applied to the design using Artificial Intelligence.

This presentation introduces SimAI for bug hunting applications. SimAI is a tool that uses machine learning to synthesize test regressions. In this work, we focus on the bug hunting problem and provide an overview of how SimAI addresses it. Finally, we provide results achieved on three distinct customer designs.

Before tapeout, there are many physical signoff items. To speed up, Innovus will not accurately calculate all the information, which leads to Innovus and signoff tools not being able to be fully matched. So, when we run signoff, itâ s common to have violations, such as IRdrop, signalEM, SI, etc. This article aims to design an automated process to obtain relevant violation results from the signoff tools, simulate the manual fixing steps, and fix the existing violations automatically. When there are many types of violations, this process can greatly reduce the development cycle of engineers.

Improving the code quality and stability is critical to stay ahead of competition. This paper presents the new methodology and tools used by the Virtuoso teams to identify and fix customer crashes. The crash rate was halved and more than 70% of customer crashes are tentatively fixed even without getting customer reproducible data. It describes ML and cloud based solutions to automatically collect crashes and assign them. Then present a set of tools used to assist the root cause analysis and finally highlight methodologies to prevent crashes in new releases.

We developed and executed a unique and Innovative Process where we got Verisium Debug community to contribute innovative ideas for Verisium Debug. It was followed with an â Innovation Sprintâ where R&D created POC for the best ideas and later made them into full features. This process strengthened our connections with the Field and contributed to our toolâ s perception. We believe other teams in cadence can leverage this process to innovate with their communities. This lecture was selected as the closing session in Haifa CIC in January 2024. It received very positive feedback in the survey that followed the event.

Design partitioning for multi-threaded simulation was explored multiple times (usually hierarchical split). In many cases designs contain passive logic (i.e., no feedback to main design): SVAs, protocol checkers, scoreboards. We suggest separating of the passive logic into secondary snapshot, completely asynchronous simulation, one way communication.

Photonic circuits disrupt the traditional design methodoligies within virtuoso. Many designers start their design in the layout, creating waveguides and optical devices directly - as a result there is often no schematic to netlist and simulate from. Additionally, waveguides play the role of both connectivity and active devices, creating new challenges for design and validation. These new aspects of circuit design resulted in productivity bottlenecks within the Virtuoso tool, leading to designers spending hours on tedious tasks. This presentation demonstrates some of the work that has been undertaken over the last few years to alleviate these bottlenecks.

The paper discusses a customer situation, where VirtualMachine+Palladium system always timed out at the VM application, as Palladium went into a waveform dumping state. The Palladium stopped its clock during waveform dumping/misc tasks, unaware of the fact that a WallClockTimer was ticking on the VirtualMachine waiting for a response from the DUT, and WallClockTimer eventually timedout, as Palladium went into a waveform dumping state. The paper discusses the innovative approach adopted to make VM aware of the Palladium's SimtimeStopState, and Slowdown/resume the WallClock time at Virtual Machine(changing the speed of time and SlowingDown VM), thus avoiding timeouts. (Patent is Filed)

This presentation will present TC1 architecture and our journey â how our chiplet reference platform for ADAS systems will jumpstart collaboration and innovation in the automotive ecosystem with customers. This direction is founded on the confluence of two seemingly contradictory industry trends: the move towards high-performance, centralized computation to enable the software-defined vehicle and the disaggregation of computation into discrete chiplets that can be independently verified and certified. A multi-chipset-based architecture including high-performance compute chiplets and lower complexity safety certified chiplets achieves both goals while enabling ecosystem members to innovate through the custom accelerator and application-specific chiplets.

We present a tool developed for Honda Japan, continuously enhanced over the past five years. Previously, Honda engineers spent weeks manually closing holes in car geometries. Our tool automates hole-closure within minutes to an hour, significantly reducing engineer time. Customer feedback highlights its robustness and 100% success rate. This tool can be used for all applications (Auto, Marine, PCB, etc.) without any geometry restrictions. The algorithm uses an octree marking process and a min-cut algorithm to create and refine closing patches. Additionally, a derived â wet-surface-detectionâ algorithm reliably identifies wet surfaces in â dirtyâ geometries. Recent improvements further enhance patch location, shape.

Wireline interconnect data-rates have been doubling consistently every 3-4 years due to increasing demand for higher connectivity speed in datacenters. With limited improvement of the electrical channels, MLSE has emerged as a key digital technique for boosting signal power in wireline links, at the price of increased latency and die area. This paper presents an low latency speculative error correction engine embedded within the DFE. It uses a simplified ML detector to correct single symbol errors before they propagate into a burst. Significant reduction of the trellis size is achieved by using soft information together with assumptions on the error distribution.

Cadence Verification IP group has a long history of using automation in the development process. With that, almost all Verification IP automated processes are targeting mainly creation of user APIs, while VIP code development is done manually. This paper presents VIP Factory â automation tool that is intend to speed up development of Verification IPs through wider introduction of automation into VIP code development process.

Knowledge of small molecule binding pockets in the proteins involved in disease conditions is a prerequisite for rational design of therapeutic molecules. For decades, it remained challenging to design therapeutics for certain life-threatening diseases simply because a small molecule binding pocket could not be identified. To accelerate the process of prediction of such cryptic pockets in target proteins, we developed computational workflows that explore conformation landscape of the protein and perform automated search of cryptic pockets from the conformational ensemble. Our methodology has been validated by successful prediction of known cryptic pockets in a wide range of protein targets.

Fidelity â CAD-Fillâ seeks to augment the Fidelity AutoSeal feature, in that it circumvents the laborious CAD healing/editting operations and produces water-tight CAD sealing geometries automatically, tremendously cutting down on the geometry cleaning times for downstream surface mesh generations and CFD simulations. In terms of geometry cleaning technologies, "CAD-Fill" stands on the shoulders of two giants: (Beta-CAE) ANSA and Fidelity AutoSeal. It retains all the major benefits of both features while eliminating their respective drawbacks, making it a strong and valuable addition to the cleaning product portfolio at Cadence.

This presentation describes the types of front-end graphical capture tools used by CreVinn (acquired by Cadence) where RTL is automatically generated from a flowchart representation created by the engineer. When engineers review the flowcharts they are reviewing the actual RTL also, as the Verilog is autogenerated directly from captured flowcharts. The purpose of this presentation is to encourage Cadence to consider developing such front-end EDA tools, either for in-house purposes or as commercial offerings.

We present a generator for scalable transmission lines. It offers a rich user interface to the user to define the cross section of the transmission line. Based on this cross section, the corresponding layout and front end PCells are automatically generated and a scalable model is produced via the EMX integration.

Design migration is a new technology used to duplicate existing chip designs in other technologies (usually smaller). Current algorithms use geometrical algorithms which focus on detailed implementation instead of capturing the global design topology intent. This presentation describes a novel approach using AI models to capture the routing topology from one design and apply it to a target design. It presents the model, the promising results and the plan for a future integration in Virtuoso

These slides present the innovative High-Speed Tx architectures for Low Swing & Low Power, Low Area applications such as DPHY v1.2. The presentation involves material from two filed patents: â Dual Mode LDO with Fast Transient Switching Between Modes for D-PHY Applicationâ 22PA102US01 â Low-Power, High-Speed Transmitterâ 24PA008US01 Above innovations resulted in power reduction of 10mW for 8D2C IP configuration & area reduction of 5600um2 in CMN Lane due to removal of CMN LDO.

Customers from the globe are required to make 3DIC designs with chiplets of multiple technologies (MTS) from the main foundries. In cooperation with TSMC and some key customers, we enhanced Spectre to handle multiple TMI and OMI model libraries, which allows multiple TMI or OMI model libraries to be simulated in the same netlist. This paper first introduces some concepts of TMI and OMI MTS simulation. It then demonstrates the usage model of TMI (OMI) MTS in Spectre and in Virtuoso/ADE. Finally, several TMI (OMI) MTS simulation results, including Electro-Photonics co-simulation and TMI aging, are presented.

To greatly reduce the development periods of the PCB design, a data-driven library is generated based on parametric rational models. With necessary parameter sampling from 2D/3D simulation results as training data, this paper defines parametric rational function as model mapping different physical design parameters to network parameters (S-/Y-/Z-parameters) that makes new modeling can be finished in seconds. With realistic design, this paper has validated effectiveness of the method.

We will present an innovative approach to address simulation failures caused by random seed issues. Our solution focuses on analyzing passing and failing coverage databases along with waveforms to identify key areas in the design where bugs may occur. This method enables precise localization of the root cause, significantly improving debugging efficiency.

Custom IC floorplan once proven through silicon for the best performance, power and area, is always preferred to be re-used by custom designers as a standard for similar design architecture â ¢ Quality constraints practiced by custom designer and their style of working by having full control on tool and automation, do not allow feasibility of fully automated commands â ¢ The implementation enables choosing an anchor block in target design, which will place other target blocks around the anchored block with same relative distance and order as present in the reference design â ¢ The presentation explains the innovative method called â Assisted Place like Layoutâ

Low latency is a critical specification for many die to die link standards that strive to provide seamless IO connectivity between chiplets. Achieving Low latency warrants optimizing the latency of both analog and digital data paths such that end-end time of flight of the data could be minimized. One of the key components contributing to total link latency is the data handoff between â digitalâ to the â analogâ . This invention focusses on optimization of the latency between data transfer from digital to analog.

Customer came to us with a requirement of improving performance of their complex environment. By utilize GCC compile and using dl_load() function on Save/Restart flow, we reduced 99% of elaboration time and reduced 4x simulation time on their environment.

This submission presents a novel framework that integrates the advantages of both message passing and transformer architectures, achieving superior performance compared to existing MP GNNs while maintaining constant space complexity. This innovation facilitates the training of large graphs using limited computational resources, such as a single GPU or even a CPU. In the application of large graph similarity comparison, this model significantly outperformed the existing product.

Clock trees are key for enabling high performance designs. Without balanced clock trees, timing closure is unachievable or very power costly. Balancing clock trees to minimize clock skew is traditionally achieved by slowing down shorter clock paths using buffer insertion or adding extra wirelength, costly transforms for clock power. In fact, a late clock path forces every clock path to become late which contributes to higher on-chip variations. This work proposes new algorithm and transforms to improve late clock paths and reduce the need for costly slow down of rest of clock tree. Experiments show 5% improvement in maximum latency.

This paper proposes a STA-based multi-physics analysis flow that fully considers the impact of temperature changes on RC values and operating voltage. Through a feedback loop, the flow automatically iterates on temperature and operating voltage until a stable state is reached where the system's operating voltage, frequency, and temperature are balanced. The entire flow is based on iHDB for data exchange and interface design, integrating multiple simulation tools into a single platform and providing a simplified user interface, greatly reducing the user's learning curve.

We present JedAI Copilot, a novel LLM-driven, powerful unified query interface, to unleash the efficiency of document understanding and coding in the EDA design flow. JedAI Copilot supports a wide variety of doc formats: RTL, logs, tool script, documents, tickets, xlsx, html, etc, and can provide high quality result in natural language. In the presentation, we introduce the challenges and motivations, our solutions (JedAI Copilot), its key components and architecture, and successful use cases in many applications: document query, doc/script quality review, document comparison, ccms ticket info extraction to increase productivity, error detection from design files, code generation & modification.